力旺電子 Briefing
IPR Notice
All rights, titles and interests contained in this information, texts, images, figures, tables or other files herein, including, but not limited to, its ownership and the intellectual property rights, are reserved to eMemory Technology Incorporated and PUFsecurity Corporation. This information may contain privileged and confidential information. Any and all information provided herein shall not be disclosed, copied, distributed, reproduced or used in whole or in part without prior written permission of eMemory Technology Incorporated or PUFsecurity Corporation.
Company Overview (公司介紹)
Overview eMemory is the global leader of embedded non-volatile memory IP.
Founding & Scale
- Founded: In 2000.
- Location: Based in Hsinchu, Taiwan.
- IPO: In 2011.
- Shipments: Over 72M wafers shipped.
- Personnel: 346 employees with 72% R&D personnel.
Intellectual Property
- Patents Issued: 1330+
- Pending Patents: 205
Key Partnerships
- Best IP Partner With TSMC: TSMC Best IP Partner Award since 2010.
Financial Highlights
Revenue Trend (Unit: NT$ 1,000)
| Year | 2005 | 2006 | 2007 | 2008 | 2009 | 2010 | 2011 | 2012 | 2013 | 2014 | 2015 | 2016 | 2017 | 2018 | 2019 | 2020 | 2021 | 2022 | 2023 | 2024 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Total Revenue | (Approx. 500K) | (Approx. 500K) | (Approx. 500K) | (Approx. 500K) | (Approx. 500K) | (Approx. 750K) | (Approx. 1M) | (Approx. 1M) | (Approx. 1.25M) | (Approx. 1.5M) | (Approx. 1.5M) | (Approx. 1.75M) | (Approx. 1.75M) | (Approx. 1.75M) | (Approx. 1.75M) | (Approx. 2M) | (Approx. 2.5M) | (Approx. 3M) | (Approx. 3M) | (Approx. 3.75M) |
- Revenue components shown in chart: Royalty (Yellow) and License/Design Revenue (Green).
Revenue and Tape-out by Technology (2002–2024 Projection)
*NTO stands for New Tape-Out *Revenue includes both licensing and royalty
| Year | NTO NeoBit | NTO NeoFuse | Revenue (USD) NeoBit | Revenue (USD) NeoFuse | Revenue (USD) PUF-based |
|---|---|---|---|---|---|
| 2002 | 3 | ||||
| 2003 | 29 | ||||
| 2004 | 40 | ||||
| 2005 | 68 | $4,217,380 | |||
| 2006 | 133 | $6,202,270 | |||
| 2007 | 220 | $9,402,479 | |||
| 2008 | 253 | $12,896,211 | |||
| 2009 | 268 | $11,695,587 | |||
| 2010 | 284 | $15,873,331 | |||
| 2011 | 254 | $15,399,098 | |||
| 2012 | 270 | $19,620,768 | |||
| 2013 | 363 | 1 | $25,436,669 | $382,084 | |
| 2014 | 371 | 3 | $31,831,985 | $328,787 | |
| 2015 | 311 | 11 | $30,943,426 | $1,080,373 | |
| 2016 | 270 | 28 | $30,247,340 | $3,636,142 | |
| 2017 | 257 | 61 | $34,619,653 | $5,238,351 | $85,000 |
| 2018 | 253 | 86 | $31,834,860 | $10,773,223 | $195,000 |
| 2019 | 226 | 109 | $27,602,332 | $14,466,279 | $434,998 |
| 2020 | 248 | 182 | $30,378,346 | $26,437,660 | $1,160,702 |
| 2021 | 252 | 259 | $32,367,560 | $44,011,223 | $4,207,209 |
| 2022 | 264 | 231 | $35,327,060 | $63,762,480 | $4,375,409 |
| 2023 | 226 | 241 | $23,251,721 | $64,276,058 | $5,279,985 |
| 2024 | 266 | 270 | $25,952,137 | $71,649,123 | $5,279,985 |
| Total | 5,129 | 1,482 | $455,100,213 | $306,041,783 | $15,738,303 |
Products & Technologies (公司產品技術)
eMemory and PUFsecurity provide OTP and PUF-based Security IP Solutions with extensive availability across various foundries and process nodes.
eMemory IP Portfolio (Technology Provider + IP Design & Service)
- NeoBit (OTP)
- NeoMTP (MTP)
- NeoFlash
- NeoEE (MTP)
- NeoFuse (OTP)
- NeoPUF (PUF)
PUFsecurity IP Portfolio (PUF-based Security IP Design & Service)
- PUFrt (Root of Trust)
- PUFcc (Crypto Coprocessor)
- PUFse (Security Element)
Evolution from OTP to PUF-HSM
Hardware Security has evolved from SecureOTP to a full PUF-Based Security Subsystem.
| Layer | Component | IP/Technology | Function |
|---|---|---|---|
| Logic Non-Volatile Memory | NeoFuse | OTP Key Storage | |
| NeoPUF | PUF Key Generation | ||
| Hardware Root of Trust | PUFrt | Crypto Engine | Foundational Security IP, Encryption + Decryption |
| Crypto Coprocessor | PUFcc | SW/FM, CPU | Complete Security IP Block, Secure Software / Firmware, Central Processing Unit |
| Security Element | PUFse | SW | Security Processor Unit, Software for Virtual HSM |
| Security Server | PUF-HSM Server | For HSM Security as a Service |
The Foundation of the Security Ecosystem
- Software Security Ecosystem: Continually changing and adapting to new threats. Relies on immutable Hardware Root of Trust.
- PUFsecurity: Provides Hardware Security For the entire lifespan of the Chip, acting as the Foundational Hardware Root of Trust for Software.
PUF Technology Concepts
PUFtrng: 100 Times Faster than Conventional TRNG
PUF-based conditioning algorithm provides high-throughput and high entropy quality.
- Conventional TRNG (Similar to Classic Cars): Dynamic Entropy (ROSC) $\rightarrow$ Post-processing $\rightarrow$ Conventional TRNG (Slower, Low throughput random bits).
- PUFtrng (Similar to New Energy Cars): Static Entropy PUF (Chip Fingerprint) + Entropy Refine Engine $\rightarrow$ PUFtrng (100x Faster, High throughput random bits).
Why PQC Needs PUF?
- PUF can efficiently generate keys with long length, which is needed for Post-Quantum Cryptography (PQC).
- PUF can efficiently provide random numbers, which are needed for anti-tampering in PQC.
How PUF-based Solutions Help PQC (PUFrt)
By integrating the PUFrt into the security subsystem, it can effectively manage the long and complex keys required for PQC algorithms.
- NeoPUF: Unique Secret
- NeoFuse OTP: Secure Storage
- TRNG: Dynamic Randomness
- Anti-tamper: Key Protection
Clients & Markets
TSMC Metrics
- Registered IP > 750 (Across nodes from 3nm to > 0.35um)
- New Tape Out Contribution (NTOs) > 2400 (Across nodes from 5-4nm to > 0.35um)
- 8" Wafer Contribution > 25M (Millions) (Across nodes from 7-6nm to > 0.35um)
Security Business Development Platforms
eMemory leverages different platforms for sales in security IPs and sub-systems.
| Platform | Partners/Clients | Activities/Focus |
|---|---|---|
| Foundry Platforms | TSMC, Intel, UMC, GF, etc. | Licensed security technology to major foundries; Co-promotional activities. |
| CPU Partners | Arm, RISC-V, Cadence, etc. | SoC customers looking for both CPU and security subsystems. |
| CSP (Cloud Service Provider) | More to come | Work with CSP and system companies for embedded security on a chip level. |
Market Application
Customers will adopt PUF-based Security Solutions in:
- CPU, AI, SSD
- DPU, DTV/STB, Wi-Fi
- FPGA, ISP, And More.
Memory Yield Improvement (SRAM/DRAM)
eMemory's security IP and OTP/MTP IP 1) ensure data security and 2) improve yield for SRAM and DRAM.
- SRAM (AI Accelerator): Embedded memory repair function to improve yield.
- DRAM (e.g. DDR5) (DIMM): Standalone memory repair function to improve yield.
- CXL Memory (CXL Memory Controller): PUF-based solutions for secure data transmission.
- Storage (SSD/HDD) (SSD Controller): PUF-based solutions for secure data storage.
SRAM Yielding Requirement:
- SRAM yield decreases as technology is scaled. To increase yield, eMemory's OTP is required.
- NeoFuse offers a smaller OTP size compared to eFuse (e.g., 64Kb NeoFuse is ~0.1mm² vs. 64Kb eFuse >1mm²).
- Repair needs 16~256Kb OTP!
Partnering for Success: eMemory and Siemens eMemory provides OTP with interface for Siemens MBIST (Memory Built-in Self Test).
- Tessent: Provides memory BISR (Built-in Self Repair) functions with BIST (Built-in Self Test) and BIRA (Built-In Redundancy Analysis).
- NeoFuse OTP: Provides defect-free OTP using BIRA, BISR and adapter to Tessent.
- New MBISR: Tessent MBISR + NeoFuse, scanning defective SRAM by word/column and logging to the OTP.
- Benefits: 1. Compact, 2. Flexible, 3. Robust.
On-System Repair for AI Accelerators MBIST offers on-system repair capabilities, essential for high-speed high-reliability applications and chiplet architecture or after system packaging (e.g., AI Servers, Automotive).
Strategic Initiatives & Plans
Future Development Focus (公司未來發展重點影片展示)
- NeoPUF – The Holy Grail of Security: Establishing an unforgeable identity for every chip, creating the ultimate foundation for zero-trust security.
- Quantum-Proof Security: PUF based HSM Edge Server for PQC Migration: Transforming hardware security into a scalable service, protecting critical data and infrastructure from cloud to edge.
- Chiplet Supply Chain Secured by NeoPUF: Extending trust boundaries to secure the future of heterogeneous computing and integration.
- NeoPUF: The Hardware Trust Anchor Powering Tomorrow's Defense Systems: Powering the trusted core of next-generation defense security.
Next Computing: Confidential Computing
- Goal: Protect data in the Virtual Memory of Multi-Core CPUs.
- Mechanism: CPU Cores and Virtual Memory have unique corresponding tag numbers.
- Tag numbers are internally randomly generated by PUFcc (Crypto Coprocessor IP).
Caliptra (Silicon Root of Trust Standard)
eMemory's root of trust IP is ready to meet Caliptra's requirements.
Caliptra Timeline:
| Date | Milestone | Description |
|---|---|---|
| September 2021 | Project Start | Founders begin the effort. |
| May 2022 | OCP Intro | Specification is formalized at Open Compute Project. |
| March 2023 | Open Source / Functional RTL | Charter is adopted at Linux Foundation. Founders contributed RTL Op8 pre. |
| August 2023 | Full Functionalities Defined | All flows are defined and are implemented in RTL. |
| October 2023 | Validation Completed | RTL, ROM are fully validated and ready for chip design-in. |
| March 2024 | Caliptra 1.0 | Complete specification, firmware coverage, countermeasures and testing. |
eMemory IP Portfolio in Caliptra Silicon RoT:
- OTP
- PUF
- TRNG
- Crypto Engine
Functions Enabled by eMemory IP:
- Unique Chip Identity: Chip Fingerprint
- Secure Attestation: Device Certificate
- Secure Boot: Boot into Trusted Operating System
Post-Quantum Cryptography (PQC) Migration
Why Migrate to PQC?
- Future-Proof Security for the Quantum Era: Eliminate risks posed by quantum computing threats.
- Adopt PQC-Ready HSM Edge Servers: Support both RSA/ECC and PQC crypto algorithms.
PQC Migration Steps & Scope Key Principles:
- Execute Clear Migration Steps
- Prioritize Critical Digital Assets
- Deploy PQC-ready HSM Edge Servers
| Step | Action | Requirement/Goal |
|---|---|---|
| Assess | Identify key databases and prioritize upgrades. | |
| Choose PQC | Select from FIPS 203/204/205 for key exchange & signatures. | |
| Ensure Agility | HSM must support PQC, ECC, RSA (e.g., TLS, IPSec). | |
| PQC Testing | Validate PQC integration via software. | |
| Migration | RSA → PQC; ECC → PQC; AES128 → AES256. | |
| Monitor | Track new database and key system to ensure stability. |
NeoPUF-based PQC Security as a Service Provides Zero-Trust NeoPUF-based PQC Security as a Service.
- Foundation: NeoPUF-based HSM Edge Server
- Service Layers: KMS (Key Management System), CMS (Certificate Management System), IAM (Identity and Access Management System).
- Input: PQC FIDO Key & Multi-Factor Authentication (MFA).
- Note: PKI: public key infrastructure / CA: certificate authority / RA: registration authority.
NeoPUF-based HSM Edge Server Applications:
- Financial Services & Banking
- E-Commerce & Retail
- Healthcare & Pharmaceuticals
- Government & Public Sector
- Telecommunications
- Cloud & Data Centers
- Automotive & Manufacturing
Chiplet Security and National Defense
Security Challenges in Chiplets
| Category | Challenge |
|---|---|
| Chiplet Supply Chain | 1. IP Piracy (IP theft) |
| 2. Malicious Parts ("Trojan” chiplets may exist) | |
| 3. Counterfeit Parts (Unauthorized chiplets can be inserted) | |
| Authentication between Chiplets | 1. Primary Components (e.g. Core / Accelerator) |
| 2. Enabling Components (e.g. I/O) | |
| 3. Supportive Components (e.g. Memory) |
NeoPUF for Supply Chain Security
| Phase | Challenge Addressed | NeoPUF Solution |
|---|---|---|
| Design & Fabrication | IP Piracy | Built-in HUK (Hardware Unique Key), eliminating the need for key injection. |
| Fab./ Packaging | Malicious Parts | Each component carries a PUF UID for device management. |
| Deployment | Counterfeit Parts | Keys & certificates generated by the PUF assist in supply chain management. |
NeoPUF-based Solutions for Chiplet Security
- HMAC (Cryptographic Accelerator): One-way symmetric authentication.
- Secure OTP (Secure Storage): For key / certificates.
- PUFrt (Hardware Root of Trust): UID / Key.
- PUFcc (Crypto Coprocessor): Two-way asymmetric authentication.
PUF: The Foundation of National Security
PUF enables defense systems to secure global multi-tier supply chains.
- Create a unique and unforgeable hardware identity for every chip.
- Provide a hardware root-of-trust, enabling secure verification, key generation, and device authentication.
- Turn each chip, drone, radio, or satellite into a trusted and traceable element of the mission system.
Applications in Defense Using PUF:
| Level | Security Focus | Applications |
|---|---|---|
| Supply Chain Level | Supply Chain Assurance (verify origin and traceability) | Anti-Counterfeiting for Military Electronics; Supply Chain Security. |
| System Level | System-Level Security (ensure trusted operation) | Secure Boot & Firmware Integrity; IoT & Sensor Network Security. |
| Device Level | Device-Level Protection (secure the hardware itself) | Device Authentication & Identification; Secure Key Generation. |
NeoPUF: Excels in National Defense
- 01 Reliable in Any Condition: Stay stable and accurate even in extreme heat, cold, or noise.
- 02 Radiation-Resistant: Unlike SRAM, its gate-oxide quantum tunneling mechanism prevents space-radiation effects from disrupting stability.
- 03 Tamper-Proof & Unclonable: Its physical structure can't be flipped or copied, making hacking or cloning nearly impossible.
- 04 Adaptable Across the Defense Ecosystem: Deployed across multiple domains such as communication, surveillance, and aerospace, ensuring consistent hardware trust foundation.
Additional Data
High-Density SRAM Need in AI
High-density SRAM is needed to increase the speed of AI accelerators for use in:
- Buffer Memory: Acts as fast intermediate storage to improve data transfer speed and reduce energy costs.
- AI Model Training: Helps store vast amounts of data for AI accelerators to access quickly to speed up training.
- Computing in Memory (CIM) for Inference: Enables in-memory computation by storing large datasets and performing computations on them without transferring data to separate processors.
NIST PQC Standards (Announced in 2024)
- FIPS 203, Module-Lattice-Based Key-Encapsulation Mechanism Standard
- FIPS 204, Module-Lattice-Based Digital Signature Standard
- FIPS 205, Hash-Based Digital Signature Standard
Contact Information
For more information, please visit:
- eMemory Website: https://www.ememory.com.tw/
- PUFsecurity Website: https://www.pufsecurity.com/