力旺電子 (eMemory) 法說會簡報

Company Overview

• Company Name: 力旺電子 (eMemory Technology Incorporated)
• Core Business: Global leader of Logic NVM (Non-Volatile Memory) and Security IP.
• Founding & IPO: Founded in 2000 and IPO in 2011.
• Partnerships: Recognized as TSMC's Best IP Partner every year since 2010 (16-Year Best IP Partner with TSMC).
• Intellectual Property:
  • 1350+ Patents Issued.
  • Expanding IP footprint with 228 pending patents.
• R&D Focus: Driven by a 342-member team with 73% R&D focus.
• Disclaimer: All rights, titles, and interests contained in this information, texts, images, figures, tables or other files herein, including, but not limited to, its ownership and the intellectual property rights, are reserved to eMemory Technology Incorporated and PUFsecurity Corporation. This information may contain privileged and confidential information. Any and all information provided herein shall not be disclosed, copied, distributed, reproduced or used in whole or in part without prior written permission of eMemory Technology Incorporated or PUFsecurity Corporation.

Financial Highlights

• Revenue Trend (Unit: NT$ 1,000):
  • Projected total revenue for 2025 is approximately NT$ 4,500,000, comprising Royalty and License/Design Revenue.
  • Historical data and projections show consistent growth in both Royalty and License/Design Revenue from 2005 to 2025.
• Revenue (USD) by Technology (Total 2002-2025 Projected):
  • NeoBit: $482,412,457
  • NeoFuse: $384,164,465 (started contributing in 2013)
  • PUF-based: $23,383,735 (started contributing in 2017)
  • Revenue includes both licensing and royalty.

Products & Technologies

eMemory, with its widely verified IP process platform, and PUFsecurity, provide OTP and PUF-based Security IP Solutions with extensive availability across various foundries and process nodes.

Core Technology: Logic Process NVM

Logic Process NVM offers solutions for Yield Enhancement, Performance Flexibility, and Fundamental Security.

• Yield Enhancement:
  • Memory repair for DRAM/SRAM
  • Image sensor recovery
  • Analog circuits trimming
• Performance Flexibility:
  • Code storage & execution
  • Product differentiation & version control
• Fundamental Security:
  • Hardware-rooted, unalterable key storage

Logic NVM vs. Traditional NVM Comparison:

Product Families & Solutions

eMemory (Technology Provider + IP Design & Service):

• NeoBit (OTP): Primarily for 8-inch Wafer Processes.
• NeoFuse (OTP): Primarily for 12-inch Wafer Processes.
• NeoEE (MTP)
• NeoMTP (MTP)
• NeoFTP (MTP)
• NeoFlash (Flash)
• NeoRRAM (Flash)
• NeoPUF (PUF)

PUFsecurity (PUF-based Security IP Design & Service):

• PUFse
• PUFcc
• PUFrt

PUF-Based Hardware Security

PUF evolves from OTP technology, providing an invisible, unique, unclonable hardware key.

• Root of Trust:
  • Secure OTP
  • TRNG (True Random Number Generator)
  • NeoPUF
  • PUFrt
• Crypto-processors:
  • PUFcc
  • PUFhsm (Hardware Security Module)
• Cryptography:
  • RSA
  • ECC (Elliptic Curve Cryptography)
  • AES (Advanced Encryption Standard)
  • SHA (Secure Hash Algorithm)
  • PQC (Post-Quantum Cryptography)
  • ... etc.
• Certifications:
  • NIST CAVP (PQC) (FIPS 203/204/205, SP 800-208)
  • NIST CAVP/ESV
  • PSA L3 RoT, L2 ready
  • SESIP L3

eFuse vs. OTP Comparison

Advanced Nodes Amplify the Structural Limitations of e-Fuse:

• As SoC functionality grows more complex, 8-16 e-Fuse blocks typically increase per SoC, significantly amplifying area and routing pressure, and requiring larger SRAM to compensate for e-Fuse limitations.
• Challenge: Growing functional requirements (e.g., code storage, configuration data, SRAM repair) drive multiple e-Fuse block deployments.
• Impact: Increases silicon area consumption, creates severe backend routing challenges, and additional SRAM overhead.

Multi-e-Fuse Architectures Impose High Costs in Area, Power, and Efficiency:

• Area Overhead: e-Fuse data must be copied to SRAM at boot due to limited read cycles and high-temperature constraints, increasing boot time and doubling memory footprint.
• Design Complexity: Distributed placement of 8-16 e-Fuse blocks complicates routing. Programming e-Fuse requires high current, adding constraints to power planning and IR drop management.
• OTP Advantages: Direct read access, no read-count or temperature limitations, full operating temperature range support.

OTP Delivers a Clear Area Advantage Beyond 4K × 8 Density:

• For a total storage capacity of 32K × 8:
  • e-Fuse Solution (16 × 2K×8): Total area ~1.92 mm² (excluding SRAM), requires additional SRAM/registers.
  • OTP Solution (1 x 32K×8): Total area 0.33 mm², not required additional SRAM/registers.
  • Conclusion: >80% area reduction with OTP, further savings in area and power.

e-Fuse vs. OTP: A Critical Choice for Advanced Nodes:

Evolution from OTP to PUF-HSM

Hardware Security has evolved from SecureOTP to a full PUF-Based Security Subsystem.

• Logic Non-Volatile Memory: NeoFuse -> NeoPUF (OTP Key Storage, PUF Key Generation)
• Hardware Root of Trust: PUFrt -> Crypto Engine (Foundational Security IP, Encryption + Decryption)
• Crypto Coprocessor: PUFcc -> SW/FM, CPU (Complete Security IP Block, Secure Software / Firmware, Central Processing Unit)
• Security Element: PUFse -> SW (Security Processor Unit, Software for Virtual HSM)
• Security Server: PUF-HSM Server (For HSM Security as a Service)

The Foundation of the Security Ecosystem

• Software Security Ecosystem: Continually changing and adapting to new threats, relies on immutable Hardware Root of Trust.
• PUFsecurity: Hardware Security for the entire lifespan of the Chip, Foundational Hardware Root of Trust for Software.

PUFtrng: 100 Times Faster than Conventional TRNG

• PUF-based conditioning algorithm provides high-throughput and high entropy quality.
• Conventional TRNG: Dynamic Entropy (ROSC) -> Post-processing -> Slower (Low throughput random bits).
• PUFtrng: Static Entropy PUF (Chip Fingerprint) + Entropy Refine Engine -> 100x Faster (High throughput random bits).

eMemory enables High-Yielding SRAM

• SRAM yield decreases as technology scales. eMemory's OTP is required to increase yield.
• Process: Obtains bad memory cell location, stores it in eMemory OTP/eFuse, takes redundant memory column to replace, then replaces and "switches" with the bad cell.
• OTP Size Comparison (NeoFuse vs. eFuse): NeoFuse offers significantly smaller area (0.1mm² for 64Kb) compared to eFuse (>1mm² for 64Kb). Repair needs 16256Kb OTP.

Partnering for Success: eMemory and Siemens

• eMemory provides OTP with an interface for Siemens MBIST (Memory Built-in Self-Test).
• Siemens Tessent: Provides memory BISR (Built-In Self Repair) functions with BIST (Built-in Self Test) and BIRA (Built-In Redundancy Analysis).
• eMemory NeoFuse OTP: Provides defect-free OTP using BIRA, BISR, and an adapter to Tessent.
• New MBISR: Tessent MBISR + NeoFuse, scanning defective SRAM by word/column and logging to the OTP.
• Benefits: Compact, Flexible, Robust.

On-System Repair for AI Accelerators

• MBIST offers on-system repair capabilities essential for high-speed, high-reliability applications, chiplet architecture, or after system packaging.
• Enables memory repair for packaged chiplets, reducing the need for large amounts of SRAM (Cache) for repair.
• Made possible with MBIST.

How PUF-based Solutions Help PQC?

• eMemory's PUF-based Root of Trust (PUFrt) helps PQC by providing:
  • Unique Secret (from NeoPUF)
  • Secure Storage (from NeoFuse OTP)
  • Dynamic Randomness (from TRNG)
  • Key Protection (from Anti-tamper)
• By integrating PUFrt into the security subsystem, it can effectively manage the long and complex keys required for PQC algorithms.

NeoPUF-based Solutions for Chiplet Security

• Cryptographic Accelerator (HMAC): One-way symmetric authentication.
• Secure Storage (Secure OTP): For key / certificates.
• Hardware Root of Trust (PUFrt): UID / Key.
• Crypto Coprocessor (PUFcc): Two-way asymmetric authentication.
• These IPs are integrated into chiplet components like Memory Die (HBM/DDR), Core Die (CPU), I/O Die (High-Speed PHY), and Accelerator (GPU/NPU) to provide comprehensive security.

Clients & Markets

• Foundry Platforms: TSMC, Intel, UMC, GF, etc.
  • eMemory licenses its security technology to major foundries and engages in co-promotional activities.
• CPU Partners: Arm, RISC-V, Cadence, etc.
  • Serves SoC customers looking for both CPU and security subsystems.
• CSP (Cloud Service Provider): More to come.
  • Works with CSP and system companies for embedded security on a chip level.

Where eMemory Fits: AI Memory System

eMemory's solutions are crucial across the AI memory hierarchy:

• SRAM (AI Accelerator): SRAM embedded in GPU/TPU/NPU.
• HBM (On-package 3D DRAM).
• DRAM (Server Memory): GDDR6/7, SOCAMM/DDR5 (Emerging).
• CXL Memory (CXL Infrastructure): Memory pooling & disaggregation.
• Storage: Storage Controllers: SSD/NVMe for AI model storage.

eMemory's Contributions:

• Memory Repair: OTP repair for embedded memory (SRAM/HBM/DRAM), MTP-based updateable DIMM configuration (DDR5/SOCAMM), cost-effective AI chip mass production, ensures HBM stack integrity, guarantees long-term data retention, operational stability under extreme AI workloads.
• PUF-based Solutions: PUF-based Root of Trust (PUFrt) establishes a hardware-anchored trust foundation, secure data transmission across CXL memory pools, protects data storage within NVMe/SSD controllers to safeguard AI models.
• OTP: Needed for trimming analog circuits in Sensors and Actuators.
• NeoFlash: To replace conventional eFlash for a much lower cost.
• Root of Trust: Provides key storage/generation, cryptographic processing to protect AI models, input data and output results, and confidential computing.

Outlook & Strategy

Advanced-Node Tape-out Landscape

• Leading-Edge Nodes (3nm-7nm):
  • 55 TOTAL TAPE-OUTS.
  • Driven primarily by AI and Advanced System-on-Chip (SoC) technologies.
  • Breakdown: Defense-related (21), AI SoC (7), SSD Controller (9), Others (18).
• Mainstream Advanced Nodes (12nm/16nm):
  • 77 TOTAL TAPE-OUTS.
  • Driven by demand in High-end Multimedia Processing and Networking sectors.
  • Breakdown: Multimedia (38), Network IC (11), SSD Controller (13), Others (15).

Caliptra Project & PQC Migration

• Why Caliptra is Important: Every datacenter chip (DPU, CPU, GPU, NIC) needs a Root of Trust. Caliptra provides this.
• Caliptra 1.0: Complete specification, firmware coverage, countermeasures and testing (March 2024).
• Caliptra 2.0: Integration of Post-Quantum Cryptography (PQC) algorithms (October 2024).
• eMemory's Role in Caliptra: eMemory's root of trust IP (OTP, PUF, TRNG, Crypto-processors, Cryptography (PQC)) is ready to meet Caliptra's requirements, enabling Unique Chip Identity (Chip Fingerprint), Secure Attestation (Device Certificate), and Secure Boot (Boot into Trusted Operating System).

PQC Migration Steps & Scope:

• Key Principles: Execute Clear Migration Steps, Prioritize Critical Digital Assets, Deploy PQC-ready HSM Edge Servers.
• Steps:
  1. Assess: Identify key databases and prioritize upgrades; select from FIPS 203/204/205 for key exchange & signatures.
  2. Choose PQC: HSM must support PQC, ECC, RSA (e.g., TLS, IPSec).
  3. Ensure Agility.
  4. PQC Testing: Validate PQC integration via software.
  5. Migration: RSA → PQC, ECC → PQC, AES128 → AES256.
  6. Monitor: Track new database and key system to ensure stability.

NeoPUF-based PQC Security as a Service

• PQC FIDO Key & Multi-Factor Authentication (MFA): Supports user authentication.
• Zero-Trust NeoPUF-based PQC Security as a Service: Comprises IAM (Identity and Access Management System), CMS (Certificate Management System), KMS (Key Management System), all underpinned by a NeoPUF-based HSM Edge Server.
• Applications: Provides security for various applications.
• Note — PKI: public key infrastructure / CA: certificate authority / RA: registration authority.

NeoPUF-based Hardware Security as a Service Ecosystem

• Strategy: Starting from a hardware-secure foundation and a software-secure platform, eMemory unlocks value by embedding security natively in every service workflow.
• Client-Side Devices: PUF-based FIDO, Bio-MFA, Smart Card.
• SaaS Application Platform (App Store): Supports enterprises (Corporate Bitcoin Reserve, Self-Signed CA Service, VIP Privacy Protection System) and end customers (Bank Bitcoin Custody, RWA Service, Prokey Ordering System, OTA Service, More Applications...).
• Security Capability Layer: IAM (RBAC), PKI (certificate management), KMS (key management), FIDO2 (WebAuthn), CMS (certificate lifecycle).
• Infra. Layer: PUF-based Network HSM (PUF-based HSM Card & Server Integration).

Security Challenges in Chiplets & NeoPUF Solutions

• Chiplet Supply Chain Challenges:

  1. IP Piracy: IP theft.
  2. Malicious Parts: "Trojan" chiplets may exist.
  3. Counterfeit Parts: Unauthorized chiplets can be inserted.

• NeoPUF for Supply Chain Security:

  • Design: Built-in HUK (Hardware Unique Key), eliminating the need for key injection, addresses IP Piracy.
  • Fab./ Packaging: Each component carries a PUF UID (Unique ID) for device management, addresses Malicious Parts.
  • Deployment: Keys & certificates generated by the PUF assist in supply chain management, addresses Counterfeit Parts.

• Authentication between Chiplets Challenges:

  1. Primary Components (e.g., Core / Accelerator): Requires High security (Anti-Tampering, Secure Storage, Unique ID, TRNG) and Two-way Authentication (Asymmetric Crypto).
  2. Enabling Components (e.g., I/O): Requires Moderate security (Anti-Tampering, Secure Storage, Unique ID, TRNG) and One-way Authentication (Symmetric Crypto).
  3. Supportive Components (e.g., Memory): Requires Basic security (Anti-Tampering, Secure Storage) and One-way Authentication (Symmetric Crypto).

Additional Data

• Cumulative Wafers Shipped: 74M+ spanning 740 production processes from 0.5µm to 2nm, with 9.8M wafers (8"-equi.) shipped in 2025.
• Registered IPs at TSMC: Projected to be > 850 by 2025, with increasing contribution from advanced nodes (3nm, 5-4nm, 7-6nm).
• New Tape Out Contribution (NTOs) at TSMC: Projected to be > 2600 by 2025, with significant growth in advanced nodes.
• 8"-Equivalent Wafer Contribution at TSMC: Projected to be > 25M by 2025, showing increasing adoption across various process nodes, particularly in 7-6nm and 16-12nm.

Contact Information

• eMemory Website: https://www.ememory.com.tw/
• PUFsecurity Website: https://www.pufsecurity.com/