Ta Liang Technology Co., Ltd. (3167) 2026Q1 法說會簡報

Company Overview

• Stock Symbol: 3167
• Capital: NTD 883,901,720
• Chairman: Laurie Wang
• General manager: Jackie Chien
• Headquarter: No. 68, Fengtian Rd., Bade Dist. Taoyuan City, Taiwan (R.O.C.)
• Factories: Bade、Nanjing、Lianshui
• TL Technology Team Function: R&D/purchasing/production/sales/service/management
• Production & Service Base:
  • Plants: Nanjing, Lianshui, Bade (H.Q. & R&D Center)
  • Service/Agent Locations: Kunshan/Wuxi (Service), Dongguan (Service), India (Service/Agent), Thailand (Service), Malaysia (Service/Agent), Vietnam (Service/Agent), Korea (Agent), Japan (Agent), China (Agent)

Financial Highlights

Income Statement (NTD Thousand)

Business Segments

• PCB BU (Printed Circuit Board Business Unit):
  • Standard & High end PCB Drilling Machine
  • Standard & High end PCB Routing Machine
  • Automation
  • Others
• Semiconductor BU (Semiconductor Business Unit):
  • Metrology Series
  • AOI Series
  • Automation Series
  • CMP Pad Metrology

Products & Technologies

PCB Drilling/Routing Products & Technology

• Drilling Machine:
  • standard
  • CCD series
  • PCB Inner layer solution
• PCB Router:
  • standard
  • CCD series
  • depth control
• Edge Coater:
  • 1 station
  • multi stations
  • Function: Ensures precise and uniform application of protective layers on glass substrates, particularly at the edges where damage is most likely. Enhances mechanical strength, prevents chipping and moisture ingress, and maintains optical clarity. Automated coating improves consistency, reduces waste, and boosts production efficiency, making it essential for high-quality glass substrate protection.
  • AR glass -light block out: Light block out coatings on AR glass reduce glare and control ambient light, improving image clarity and contrast. Precise application ensures a balance between transparency and light blocking for better visual experience.
• PCB Inner layer Thickness Metrology -TM2:
  • Patent: (TW)I768701 / M627729 / I792823 / M622593, (CN) 6252475 / 16503982 / 16861153 / 9180563 / 15164943
  • Features:
    • TL developed controller
    • PCB Thickness measurement module
    • Inner layer depth measurement module
    • For AI servo board, to solve the problem of unstable lamination, and excessive error between theoretical and actual value of target layer
    • Coordinate with CCD back drilling machine, to achieve high precise depth control capability
• PCB Inner layer Thickness Metrology -TM3:
  • Patent: (TW)I768701 / M627729 / I792823 / M622593, (CN) 6252475 / 16503982 / 16861153 / 9180563 / 15164943
  • Features:
    • TL developed Controller
    • Board Thickness Measurement Module
    • Inner Layer Trace Depth Module
    • Overcomes excessive deviation between actual and theoretical non-break positions caused by unstable lamination quality in AI server boards.
    • Integrates data with CCD backdrill machining to achieve highly precise alignment and depth-controlled drilling capability.
• PCB Inner layer Thickness Metrology -TM4 (Multiple Axis High-Efficiency Inner Layer Metrology):
  • Description: A newly developed multiple-axis high-efficiency measurement machine designed for inner layer metrology. It delivers industrial-scale throughput with precision and speed optimized for mass production environments. TM4 combines advanced motion control and measurement technologies to achieve rapid, accurate copper feature analysis, significantly enhancing production efficiency and quality control.
  • Outline dimension (approx.): 467822902149 (LWH)
  • N.W. (approx.): 11000 KG
• TM Function Introduction (Thickness Metrology):
  • Auto lighting sourcing change system: Auto light source changing by controller to solve the board surface reflection issue.
  • Tool cleaning: Tool auto cleaning to reduce the measurement error by dust pollution issue on tool.
  • Sampling hole check: For production efficiency, can set up hole check coverage and sampling rate.
• Key Capability: TL is the one and only in the industry capable of achieving residual copper approaching 0 mil!
  • Required Precision:
    • (1) PTH and Backdrill Hole Center Alignment Accuracy: D+10mil, D+8mil, D+6mil
    • (2) The residual copper length at the designated backdrill copper layer: 7±5 mil, 6±4mil, 6±3mil, 5+3(-2)mil
  • TL capability (for D+4mil): 2±2mil, Cpk > 1.67

Semiconductor Products & Technology

• Product Line-up Overview:
  • Front end process (Wafer fabrication): Wafer clean, Probe, test, Lithography, etch, implant
  • Middle end process (Wafer level packaging): Singulation, Die stacking, Bump placement, Reconstitution, Redistribution
  • Back end process (Assembly and packaging): Singulation, Wire bond, Die attach, Overmold/Underfill/Encapsulation
• Metrology Series: Wafer Trim-gap/Edge Profile Metrology
• AOI Series: Wafer Form AOI Machine
• Automation Series: Carrier Transfer Machine
• Advance Package-3D/2.5D Fabric:
  • 3D Si Stacking:
    • TSMC-SoIC®
    • SoIC-P: Bumped, pitch: 16-25µm
    • SoIC-X: Bumpless, pitch: < 9µm
  • Advanced Packaging:
    • CoWoS® -> CoWoS-S (Si Interposer), CoWoS-L/R (RDL Interposer)
    • InFO -> InFO-PoP, InFO-2.5D
    • TSMC-SoW™ -> SoW-P, SoW-X
  • Definitions: CoWoS: Chip on Wafer on Substrate, PoP: Package on Package
• CoWoS (2.5D Fabric) - As is (Technology Platform for HPC / AI TODAY): HBM, SoC, HBM on Interposer, on Substrate.
• 3D IC Solution-CoW:
  • HBM Incoming AOI
  • Wafer Cosmetic AOI/Warp Metrology
  • Wafer Flux Jetting AOI
  • Wafer Die Bond AOI
  • Wafer Underfill AOI/Fillet-height Metrology
  • Wafer Edge Die AOI
  • Wafer Molding AOI/DUC/Thickness Metrology
  • Wafer IPD Die Bond AOI
  • EFEM+Buffer
• 3D IC Solution-(CoW)oS:
  • Flux Jetting AOI
  • Die Bond AOI
  • R2R AOI(FVI)
  • Bonding Tool Metrology Platform
• CoWoS (3D Fabric) - To be (Technology Platform for HPC / AI TOMORROW): Large interposer + embedded components (active die + LSI + IVR, etc.) including High Performance Memory, 3D Stacking / SoIC (Chip 1, Chip 2, Chip 3), Co-Packaged Optics (Fiber), Si Photonics, RDL Interposer (Active, LSI, IVR, Passive), Substrate.
• 3D IC Solution-SoIC:
  • CMP Pad Metrology
  • Step-height Metrology
  • Bonding Wafer Edge Metrology
• 3D IC Solution-FOPLP(COP):
  • FOPLP Warpage Metrology
  • CoPoS Bond Shift_Edge Profile Metrology

Patent Information

PCB Inner layer Thickness Metrology - Patent Granted

PCB Inner layer Thickness Metrology - Pending Patent

Clients & Markets

• Customers:
  • tsmc (台灣積體電路製造股份有限公司 Taiwan Semiconductor Manufacturing Company, Ltd.)
  • VIS (世界先進)
  • ASE GROUP (日月光集團)
  • SPIL (矽品精密)
  • Powertech (PTI Technology Inc.)
  • WNC (Wistron NeWeb Corp.)
  • KYEC
  • LINGSEN
  • igiant

Outlook & Strategy

Future Outlook & Guidance (2026, Mar.)

• High-end Machine with CCD (Units):
  • 2023: Shipped 72
  • 2024: Shipped 169
  • 2025: Shipped 501
  • 2026 (Outlook): Shipped 139, Confirmed 456, On going 205 (Total 800 units)
• PCB Inner Layer Measurement Machine (Units):
  • 2025: Shipped 27
  • 2026 (Outlook): Shipped 7, On going 20, On going 45 (Total 72 units)

Additional Data

Disclaimer

• The predictive information mentioned in this presentation, including operational outlook, business situation, etc., is obtained by the Company through internal and external sources.
• The company's actual operational results that may occur in the future due to factors including but not limited to market competition and the conditions of international economy.
• The outlook for the future in this presentation is the Company's external views until now. For these views, if there are updates or adjustments in the future, the Company is not responsible for reminding or updating again at any time.