WinWay Technology 法說會簡報

Company Overview

WinWay Technology (穎崴科技) is a trusted partner in semiconductor testing.

Products & Technologies

The Evolution of Co-Packaged Optics (CPO) Advanced Testing Methodologies for Silicon Photonics

• CPO (Co-Packaged Optics): An advanced packaging technology integrating optical engines directly with ASICs, reducing distance and improving performance.
  • Benefits:
    • Speed Evolution: From Gbps to Tbps (800G to 1.6T ~ 6.4T).
    • Energy Efficiency Leap: Saving Over 50% Power Consumption (20 pJ/bit to below 5 pJ/bit).
    • Spatial Optimization: Chip-level Packaging Revolution (reducing latency by over 15%).
  • Architecture: Consists of Optical Engine (PIC, EIC), HBM, ASIC, Interposer, Substrate, PCB, Fiber Array Unit (FAU), Fiber, and External Laser Source.
• CPC (Co-Packaged Copper): An alternative co-packaging approach using copper interconnects.
  • Characteristics: Longer electrical Path (cm level), Hot-swappable & field replaceable, Higher power consumption, Mature ecosystem & cost-effective solution.
• Photonic Integrated Circuit (PIC) Blueprint:
  • Tx Path: Source (Light Generation) → Modulator (Data Writing) → Routing (Waveguides) → WDM (Multiplexing) → Coupler (Off-Chip) → Fiber.
  • Rx Path: Fiber → Coupler (On-Chip) → Routing → WDM (Demultiplexing) → Photodetector (Conversion) → Electrical Output.
  • ASIC Data drives the Modulator Driver.
• Light Source Matrix (Step 1):
  • DFB Laser (Distributed Feedback): Highly Stable wavelength, narrow linewidth. Ideal for standard 1310nm/1550nm telecom.
  • VCSEL (Vertical-Cavity Surface-Emitting Laser): Low cost, easy to form arrays. Ideal for short-reach data centers. Limitation: Less suited for long-reach / high-power.
  • Comb Laser: Crucial for 102.4T CPO. Generates multiple precise wavelengths from one device, enabling massive WDM density.
• Modulator Showdown (Step 2):
  • MZM (Mach-Zehnder):
    • Footprint: Large (1-3 mm)
    • Bandwidth: High
    • Thermal Stability: High
    • PAM4 Linearity: Excellent
    • Yield / Maturity: Highest (10+ Yrs)
    • Customers: Broadcom / Intel / Marvell / Lightmatter / Cisco
  • MRM (Micro-Ring):
    • Footprint: Micro (10-20 um)
    • Bandwidth: Medium
    • Thermal Stability: Critical (Requires TEC)
    • PAM4 Linearity: Moderate
    • Yield / Maturity: Medium
    • Customers: nVIDIA / AyarLabs
  • EAM (Electro-Absorption):
    • Footprint: Small (50-100 um)
    • Bandwidth: Medium
    • Thermal Stability: Medium
    • PAM4 Linearity: Poor
    • Yield / Maturity: Medium
    • Customers: Coherent / Lumentum / Intel
• Routing The Light (Step 3): Utilizes waveguides with Total Internal Reflection (TIR).
  • Power Splitters (MMI: Multimode Interference): Input Light (Cyan) → MMI Mixing Region → 4x Equal Output Light (Cyan).
• Wavelength Division Multiplexing (WDM) (Step 4): Uses a prism to multiplex different wavelengths (e.g., 1270 nm to 1410 nm).
  • Target KPI: Crosstalk must be maintained at -20 dB.
• I/O Coupling Strategy (Step 5):
  • Grating Couplers: Light enters/exits vertically. High insertion loss, wavelength sensitive. Advantage: Enables wafer-level testing (testing from the top before dicing).
  • Edge Couplers: High bandwidth, ultra-low insertion loss (<1.0 dB). Polarization insensitive. Ideal for 128-core FAU. Challenge: Demands extreme sub-micron alignment precision.
• Optical Engine Design:
  • 2D: Wirebond (EIC, PIC, Substrate)
  • 2.5D: EIC, PIC, Interposer, Substrate
  • 3D-WB/FC: Wirebond (EIC, PIC)
  • 3D Hybrid integration -TSV or Fan-Out: Hybrid Bonding (EIC, PIC, Interposer, Substrate)
  • 3D Hybrid integration -Hybrid bonding: Hybrid Bonding, TSV (EIC, PIC, Interposer, Substrate)
  • 3D-Monolithic: EPIC, Substrate
  • Optical Engine Connector examples: CORNING, Teramount, SENKO.
• Single Mode Fiber (SMF): The only choice for CPO due to silicon photonics waveguide being single-mode.
  • Benefits: Supports only 1 fundamental mode, Maintains signal over 2 km+, Native match with SiPh waveguide.
  • Result: Enables 200 Gbps+ over 2 km+, ideal for CPO deployment.
• Active Alignment: Critical for FAU.
  • Challenges: Fiber Roundness (≤0.8μm), Core Concentricity (≤0.5µm), Fiber Size (±0.71.0μm), V-groove Angle (±0.3°), V-groove Depth (±0.51.0μm), V-groove Pitch (±0.3~0.5µm).
  • Tolerance Stack-up: 3.8µm | 42% of core diameter.
  • Tools: Multi-Axis Photonics Alignment System, Hexapod, Piezo System for Nano positioning and Fiber Alignment.
• CPO Production Assessment:
  • Solution 1 Golden FAU (Fixed Reference Focusing): Establish Golden Device → Establish Golden FAU → Move All FAUs to Reference Position → Verify Focusing Efficiency.
  • Solution 2 Self-align (Auto Focus Calibration): Measure Intrinsic Component Variation → Build Auto Calibration Model → Auto Focus Calibration → Verify Focusing Efficiency.
• CPO Production Bottleneck:
  • Precision Packaging & Lasers: Sub-micron alignment.
  • Lack of Standardization: Different form factors (NVIDIA, QSFP, Intel).
  • Maintenance & Serviceability: External Laser Module, Downtime ↑ Cost.
  • Yield & Cost Risk: High costs, potential low yield.
• Co-Packaged Optics Test Flow:
  • Wafer Level → Die Level:
    • Components: EIC/PIC Wafer, EIC/PIC Die.
    • Testing: WLCSP Fine Pitch Probe Head (EIC/PIC Wafer test).
    • Methodology: Electrical at TOP / Optical at BTM. Electrical Test Instrument (DC / RF / BERT), Optical Test Instrument (Laser / OSA / Power Meter).
  • Package Level:
    • Components: Optical Engine, CPO Substrate.
    • Testing: Optical and Electrical Test Socket (Optical Engine), Double Sided Probing System.
    • Methodology: Active alignment, Passive alignment, Direct with FAU.
  • Module Level:
    • Components: ASIC, PIC, EIC, OE, CPO Module.
    • Testing: HyperSocket™.
    • Methodology: Pick & Place, Place FAUs, Plug All FAUs, Plug & Play.
• WinWay's Innovative Test Solution: HyperSocket™:
  • Requirements: Package Size > 100 X 100 mm², Pin count > 10,000 pin, Device Warpage > 0.4 mm, High Current Density > 6 A, SACQ (Frequent Clean) ~10 TD, Solder Ball Melting, Probe bent and worn out issue.
  • Advantages over Conventional Test Interface (Elastomer/Spring probe):
    • Significantly increased contact surface.
    • Less and stable contact resistance (↓30%).
    • Higher current carrying capacity (↑30%).
    • Less joule heat generation (↓30%).
    • No housing warpage of spring probe socket.
    • Lower total test cost of ownership (Factory operation, Hardware, Maintenance, Test interface including Change Over Kit, Socket, PCB).
  • HyperSocket™ Models:
    • Hyper-UF: For Frequent Clean, Solder Ball Melting.
    • Hyper-LF: For Ultra Large Package, High Pin Count.
    • Hyper-DH: For High Current Density, Probe Bent.
    • Hyper-Liquid: Under Validation, for Extremely High Power (> 2500W).
  • Patent NO.: TWI862047, TWI922268, TWI901181, TWI862191, TWI884802, CN220584352, TWI901161, TWI923382, US(Granted).

Clients & Markets

Optical Industry M&A Wave in the AI Era

• Nov 2024: Celestial AI acquires Rockley Photonics IP ($20M, SiPho IP consolidation).
• Dec 2025: Marvell to acquire Celestial AI ($5.5M, Optical scale-up for AI).
• Feb 2025: Nokia acquires Infinera ($2.3B, Optical networking & DCI).
• Apr 2026: Credo to acquire DustPhotonics ($1.3B, SiPho PIC vertical integration).
• May 2025: AMD acquires Enosemi (Undisclosed, SiPho PIC for CPO).
• Apr 2026: Marvell acquires Polariton Technologies (Undisclosed, Plasmonics + SiPho modulation).
• Total M&A value: ~$10B+.

Chipmakers & Hyperscalers Back Photonics

• Oct 2024: Google Ventures et al. → Lightmatter ($400M, CSP → Photonic Computing).
• Feb 2026: MediaTek → AyarLabs ($90M, IC Design → Optical I/O).
• Oct 2024: Cisco · NVIDIA → Xscape Photonics ($44M, CSP/Networking + IC → DWDM).
• Mar 2026: NVIDIA → Lumentum ($2.0B, IC Design → Laser / SiPho).
• Dec 2024: AMD · Intel · NVIDIA → AyarLabs ($155M, IC Design (joint) → Optical I/O).
• Mar 2026: NVIDIA → Coherent ($2.0B, IC Design → Laser / Networking).
• Total investment value: ~$4.7B+.

Silicon Photonics Supply Chain

• CSP (End Customer): NVIDIA, AWS, Microsoft, Meta, ByteDance.
• SOI Wafer (Photonic Wafer): soitec, ShinEtsu, SIMGUI, Intelli EPI.
• Connector: TAN, SCONEC, SENKO, samtec, SIEMON, Amphenol, 睐芯科技, LSI LightSense.
• Testing: WinWay, MPI Corporation, HON PREC, Chroma.
• PIC Design & EDA: IBM, intel, sicoya, MACOM, Juniper, CISCO, SiFotonics, POET, Ansys, AyarLabs, FUJITSU, MARVELL, LUMENTUM, Infinera, HUAWEI, RANOVUS, cadence, SKORPIOS, OpenLight, SYNOPSYS.
• Foundry: intel, Tower, A silex, GlobalFoundries, SAMSUNG UMC, ST, Acacia.
• EIC & DSP Design: BROADCOM, COHERENT, LUMENTUM, MACOM, ciena, Infinera.
• Light Source (from EPI wafer): LandMark, COHERENT, SUMITOMO ELECTRIC, Intelli EPI, IQE, NICHIA.
• Fiber: CORNING, YOFC, SUMITOMO ELECTRIC, FURUKAWA ELECTRIC, 富通集团, FUTONG GROUP, FiberHome, prysmian, ZTT, Fujikura.
• ELS: FURUKAWA ELECTRIC, BROADCOM, LUMENTUM, COHERENT, SUMITOMO ELECTRIC, TE, O-Net Technologies.

Outlook & Strategy

Co-Packaged Optics Trend

• ~2016: Pluggable Optics (100% Cu)
• 2023: OBO (On-Board Optics) (80% Cu + 20% Optics)
• 2025: NPO (Near-Packaged Optics) (50% Cu + 50% Optics)
• 2027: 2.5D CPO (COUPE Switch) (20% Cu + 80% Optics)
• 2030~: 3D CPO (COUPE XPU) (100% Optics)
• Key Metrics Evolution:
  • Bandwidth: 800G → <1.6T → <3.2T → <6.4T → 12.8T
  • Power Use: 1x → ~0.8x → ~0.6x → <0.5x → <0.1x
  • Latency: 1x → <0.75x → <0.5x → <0.1x → <0.05x
• Source: Counterpoint Research《矽光子與共同封裝光學(CPO)報告》

Key Foundries of Silicon Photonics and CPO (2025-2029 Roadmap)

• TSMC:
  • 2025: Mass Production (Platform: COUPE, PIC Node: 65nm, EIC Node: 7nm or below, Package: SoIC-X).
• SAMSUNG:
  • 2026: Platform: Samsung Electronics SiPH, PIC Node: 300mm SOI, EIC Node: SF4U/SF2Z, Package: Vertical Integration.
• Intel:
  • 2026: CPO (Optical I/O), Platform: OCI, PIC Node: Dedicated SiPH Node, EIC Node: Advanced CMOS, Package: 2.5D/3D Packaging.
  • 2029: TBD.
• GLOBAL FOUNDRIES:
  • 2025: Mass Production (Silicon Photonics Process, Platform: Fotonix, PIC Node: 45nm RF-SOI, EIC Node: EIC/M RF-SOI (EIC/PIC Monolithic), Package: Monolithic).
• UMC:
  • 2026: Dev./Validation.
  • 2027: Risk Pilot (Silicon Photonics Process, Platform: iSiPP300, PIC Node: 300mm SOI (IMEC Licensed), EIC Node: Paired with Logic Foundry, Package: Heterogeneous Integration).
• Source: DIGITIMES, 2026/04

CPO Roadmap

• Bandwidth Progression: 800G → 1.6T/3.2T → 6.4T/12.8T.
• Packaging Evolution: Packaging → Pluggable → CPO Switch → XPU Optical IO.
• Optical Engine Evolution: OE (Optical Engine) → 100G MZM → 200G MZM/MRM → 400G CWDM/DWDM.
• Fiber/FAU Evolution: 8X → 16X → 32X → 64X → 160X.
• XPU Optical IO Components: Optical Engine (OE), Switch, Substrate, XPU HBM, Interposer, 160X fiber links.
• Source: TSMC

The I/O Interface Evolution

• The Past: Electrical Interface.
• The Present: Electro-Optical Interface.
• The Future (102.4T+): Co-Design Architecture (Optical Alignment + Thermal Isolation + Signal Integrity).

Future Technical Challenge

• A. Mechanical Extremes:
  • Package Size > 100 mm up to 200mm.
  • Pin Count > 10,000 pins up to 50,000 pins.
  • Key Challenge: Warpage up to 0.6mm.
• B. Electrical Performance Barriers:
  • Signal Speed 224Gbps PAM4 and beyond.
  • Key Challenge: Signal Integrity, Crosstalk.
• C. Thermal Density Crisis:
  • Power Consumption > 4000W per device.
  • Key Challenge: Thermal Runaway / Solder Melt.
• Technical Development Direction to “Optics": Evolution from mechanical machining accuracy to multi-physics coupled design, encompassing mechanical integrity, electrical performance, thermal management.

Heterogeneous Integration: CPO is the path to success in near future

• Problem with Organic Substrates: Thermal / Mechanical Instability, Electrical Loss, High CTE Mismatch Silicon (Causes Warping & Misalignment), High Dielectric Loss.
• Glass as Breakthrough Solution: Superior Stability, Pristine Electrical Performance, Advanced Integration, Near-Perfect CTE Match to Silicon (Ensures Sub-Micron Alignment).

CPO Market Trends & Challenges

• Market Trends (2025-2030):
  • 2025: nVIDIA: First 1.6T CPO switch.
  • 2026: Spectrum-X(3.2T) mass production.
  • 2027: Optical - Copper coexist.
  • 2028: Scale-up expansion.
  • 2029: Ecosystem maturity.
  • 2030: CPO mainstream.
• Golden Window (2026-2028): For ASIC platform flexibility. One ASIC supporting both CPO and CPC —Scale-up via CPO for performance, Scale-out via pluggable for flexibility.
• NVIDIA SIGNALS:
  • 1.6T CPO saves 180MW at million-GPU scale.
  • Spectrum-X: 5x efficiency, 2Tb/s, 10x reliability.
  • CPO and copper coexist, layered deployment.
• FUTURE TRENDS:
  • Scale-up is the main battlefield.
  • Adoption: coexist → expand → mainstream.
  • ELS architecture, DSP-free design.
• CORE CHALLENGES:
  • Thermal & yield: one defect kills package.
  • Serviceability: operations SOP rebuilt.
  • Standards & cost: ecosystem immature.

WinWay is Ready for CPO & CPC Testing

• Offers advanced package test solutions for both Co-Packaged Copper (CPC) and Co-Packaged Optics (CPO) architectures, covering HBM, ASIC, Interposer, Substrate, and PCB.

Additional Data

GPU Architecture AI Chip Roadmap (2026-2035)

• GPU Die Size: 728 mm² (2026) → 750 mm² (2029) → 700 mm² (2032) → 600 mm² (2035).
• GPU Power: 800 W (2026) → 900 W (2029) → 1,000 W (2032) → 1,200 W (2035).
• # of GPU Dies: X2 (2026) → X4 (2029) → X4 (2032) → X8 (2035).
• # of HBM Stack: HBM4 X8 (2026) → HBM5 X8 (2029) → HBM6 X16 (2032) → HBM7 X32 (2035).
• HMB Power per Stack: 75 W (2026) → 100 W (2029) → 120 W (2032) → 180 W (2035).
• Interposer Die Stack: 2,198 mm² (2026) → 4,788 mm² (2029) → 6,014 mm² (2032) → 9,245 mm² (2035).
• Total Bandwidth: 16/32 TB/s (2026) → 48 TB/s (2029) → 128/256 TB/s (2032) → 1,024 TB/s (2035).
• Total HBM Capacity: 288/384 GB (2026) → 400/500 GB (2029) → 1,536/1,920 GB (2032) → 5,120/6,144 GB (2035).
• Total Power: 2,200 W (2026) → 4,400 W (2029) → 5,920 W (2032) → 15,360 W (2035).
• Chip heat density design reference: 1.1~2 W/mm².
• Source: KAIST TERALAB

The 448G Electrical Wall

• Copper Channel Loss: Insertion loss approaches -10dB on just 1 inch of premium dielectric at 112 GHz Nyquist.
• The Skin Effect Limit: At > 100GHz, skin depth drops below 0.2 um.
• Dielectric Loss Multiplier: Loss scales linearly with frequency.
• DSP Power Explosion: Compensating for physical loss requires ADC sampling > 224 GS/s.

Contact Information

• Email: sales@winwayglobal.com
• Phone: +886 7 361 0999 / +886 3 656 8282
• Website: www.winwayglobal.com