力旺電子 (eMemory) [time:Latest] 法說會簡報

Company Overview

eMemory leads the global market in Logic NVM and PUF-Based Security IPs.

Key Metrics & Achievements:

• 79M+ Cumulative Wafers Shipped: Spanning 772 production processes from 0.5µm to 2nm, and 5M wafers (8"-equivalent) shipped in 2026 H1.
• 1370+ Patents Issued: Expanding our IP footprint with 221 pending patents, driven by a 339-member team with 73% R&D focus.
• 16-Year Best IP Partner with TSMC: Founded in 2000 and IPO in 2011. Recognized as TSMC's Best IP Partner every year since 2010.

Intellectual Property Rights Statement: All rights, titles and interests contained in this information, texts, images, figures, tables or other files herein, including, but not limited to, its ownership and the intellectual property rights, are reserved to eMemory Technology Incorporated and PUFsecurity Corporation. This information may contain privileged and confidential information. Any and all information provided herein shall not be disclosed, copied, distributed, reproduced or used in whole or in part without prior written permission of eMemory Technology Incorporated or PUFsecurity Corporation.

Financial Highlights

Revenue Trend (Unit: NT$ in Million)

• 2005: ~100 (License/Design)
• 2010: ~300 (License/Design: ~200, Royalty: ~100)
• 2015: ~500 (License/Design: ~300, Royalty: ~200)
• 2020: ~1500 (License/Design: ~500, Royalty: ~1000)
• 2025 (Forecast): ~3500 (License/Design: ~1000, Royalty: ~2500)

Products & Technologies

eMemory's IP portfolio is built on two pillars: OTP as the foundation and MTP for scalable integration.

Core Concept: Embedded NVM with Logic Process

• Volatile Memory (e.g., RAM): Power Off, Data LOST
• Non-Volatile Memory (e.g., Flash/Storage): Power Off, Data STAYS
• Embedded Memory (eNVM): Faster, More Efficient, Saves Space (Integrated eNVM within Main Processor SoC)
• External Memory: Slower, Higher Power (External Memory connected to Main Processor SoC via Data)
• What eMemory Does: License IPs to Foundries and Chip Designers. Key: Enables eNVM in standard logic processes, WITHOUT extra costly steps. (Cost-Effective, Scalable). Product: Logic-Compatible eNVM IP.

Key Technology Types

• One-Time Programmable (OTP):
  • NeoBit (8-inch)
  • NeoFuse (12-inch)
  • Key Uses: Memory repair for DRAM/SRAM, Image sensor recovery, Analog circuits trimming.
• Multiple-Time Programmable (MTP):
  • NeoFlash
  • NeoMTP
  • NeoEE
  • Embedded ReRAM
  • ASIC Memory
  • Key Uses: Firmware Updates, Data Logging, Flexible Product Configuration.
• Anti-Fuse Technology (OTP): Permanent, difficult-to-tamper connection (better than standard fuse). Highest security.
• NeoPUF (Physical Unclonable Function): Uses unique microscopic variations to generate keys ON-DEMAND, not stored. Ultimate root of trust.

Technology Portfolio Timeline

• Before 2005: NeoBit (OTP)
• ~2005-2010: NeoMTP (MTP), NeoFlash
• ~2010-2015: NeoEE (MTP), NeoFuse (OTP)
• ~2015-2020: Embedded ReRAM, NeoPUF (PUF)
• ~2020-Present: PUFrt, PUFcc, SecureOTP, PUFhsm

Evolution from OTP to PUF-HSM

eMemory evolves from OTP technology into integrated PUF-based security subsystem.

• Logic Non-Volatile Memory:
  • NeoFuse: OTP Key Storage
  • NeoPUF: PUF Key Generation
• Hardware Root of Trust:
  • PUFrt: Foundational Security IP
  • Crypto Engine: Encryption + Decryption
• Crypto Coprocessor:
  • PUFcc: Complete Security IP Block
  • SW / FM: Secure Software / Firmware
  • CPU: Central Processing Unit
• Security Element:
  • PUFse: Security Processor Unit
  • SW: Software for Virtual HSM
• Security Server:
  • PUF-HSM Server: For HSM Security as a Service

Multiple-Time Programmable (MTP) Memory

• Density Variety: Scalable storage configurations, Optimized silicon footprint, Versatile capacity range (Bits to Mb).
• High Endurance: Optimized write/erase cycles, Enhanced data retention reliability, Extended application operational lifespan.
• Process Integration: Seamless standard logic embedding, Foundry-ready ASIC integration, Zero-mask overhead implementation.

Anti-Fuse OTP vs. e-Fuse

• e-Fuse: Physically Visible: Vulnerable to Reverse Engineering.
• Anti-Fuse OTP (NeoFuse): Physically Invisible: Resistant to Physical Attacks.
• Applications: Display Driver, PMIC, Sensor IC, Camera, MCU, Multi-Media, Automotive, RFID Tag, DRAM, Connectivity.
• Arm RSS (Runtime Security Subsystem) Endorsement:
  • Field-Programmable RSS Support: Enables secure storage of confidential code and data within the Runtime Security Subsystem.
  • High-Density Efficiency: Optimizes area for large arrays with seamless, low-overhead PUF integration.

e-Fuse Bottlenecks

• Area Overhead: Mandatory SRAM buffering doubles the memory footprint due to read limitations.
• Design Complexity: Scattered multiple e-Fuse block layouts trigger severe routing and power grid challenges.
• Context: Diverse functional needs in advanced-node SoCs (e.g., ROM code, key storage) drive the mandatory use of multiple e-Fuse blocks.

OTP Area Efficiency

eMemory's OTP outperforms e-Fuse in area efficiency beyond 4K×8 densities.

• Example: 32K x 8 Density
  • 16 x 2K×8 e-Fuse: Total Area: 1.92 mm² (excluding SRAM)
  • 1 × 32K×8 OTP: Total Area: 0.33 mm²
• Comparison:
  • Number of Macros: e-Fuse: 16 Macros; OTP: 1 Macro (OTP Advantage: Single-macro simplicity)
  • Total Area: e-Fuse: ~1.92 mm²; OTP: 0.33 mm² (OTP Advantage: >80% Area reduction)
  • Additional SRAM: e-Fuse: Required; OTP: Not required (OTP Advantage: Zero buffer SRAM requirement)
  • Design Effort: e-Fuse: High (Scattered); OTP: Low (Centralized) (OTP Advantage: Simplified layout & routing)

Hardware Root of Trust (HRoT)

eMemory provides the foundational Hardware Root of Trust that secures the entire software stack throughout the chip's lifespan.

• Software Security Stack:
  • Core Function: Dynamic adaptation to new threats
  • Key Attribute: Continuous evolution
• Hardware Root of Trust:
  • Core Function: Foundational trust for software
  • Key Attribute: Immutable permanence

True Random Number Generator (TRNG)

eMemory's PUFtrng delivers 100x faster performance and superior entropy quality via PUF-based conditioning algorithms.

• Conventional TRNG: Dynamic Entropy (Ring Oscillator) -> Low throughput random bits, Slower.
• PUFtrng: Dynamic Entropy (Ring Oscillator) + Static Entropy (PUF) -> High throughput random bits, 100x Faster.

Post-Quantum Cryptography (PQC)

eMemory provides NIST-compliant hardware foundations to secure data against future quantum computing threats.

• Quantum Threat: Conventional RSA and ECC encryption are vulnerable to future Shor's algorithm attacks by quantum computers.
• NIST Standards: Official FIPS 203/204/205 and SP 800-208 define the mandatory PQC baseline for global industries.
  • The Open PQC Standardization Project Launched: Dec-16
  • PQC Migration Factsheet Released: Aug-23
  • NIST First Set of PQC Algorithms Standardized: Aug-24
  • Major CSP's 2029 Q-Day Timeline Accelerated: Mar-26
• eMemory Achievements: Our PUFPQC attains full NIST coverage, securing the chain of trust from physical PUF to PQC algorithms.

Clients & Markets

Security Business Development

eMemory drives security IP adoption by collaborating with leading foundry, processor, and cloud service providers.

• Foundry Platforms (TSMC, Intel, UMC, GF, etc.):
  • Technology Licensing: Providing security IPs to leading global foundries.
  • Co-marketing Activities: Reaching diverse customer bases through joint promotional efforts.
• CPU Partners (Arm, RISC-V, Cadence, etc.):
  • System Integration: Addressing SoC customer needs for pre-integrated CPU and security subsystems.
  • Architectural Alignment: Collaborating with major processor providers like Arm and RISC-V.
• Cloud Service Providers (CSPs) (Microsoft, Meta, Google, Amazon, etc.):
  • Hardware-to-Cloud Security: Working with CSPs on embedded security requirements at the chip level.
  • Root of Trust Solutions: Developing foundational security for systems like AWS, Meta, and Azure.

Standards Drive Hardware-Based Security

• OPEN Compute Project® Caliptra: Driving an open standard for silicon root of trust.
• FIDO® ALLIANCE: Using asymmetric public/private key encryption technology and device ID to achieve fast and secure access to the network.

Caliptra Hardware Root of Trust (RoT)

eMemory's RoT IP is fully ready to meet the hardware security requirements of the Caliptra specification.

• Caliptra-compliant IPs are designed to be integrated into a wide range of high-performance Data Center and Edge components:
  • Compute: CPUs, GPUs (Accelerators)
  • Storage: SSD Controllers
  • Networking: NICs (Network Interface Cards), SmartNICs, DPU
  • Custom Silicon: ASICs, SoCs
• eMemory IP Portfolio (for Caliptra): OTP, PUF, TRNG, Crypto-processors, Cryptography (PQC).
• Core Security Capabilities: Unique Chip Identity, Secure Attestation, Secure Boot.

Caliptra Drives Broader RoT Adoption

Caliptra is driving broader RoT adoption across data center infrastructure, creating new opportunities for eMemory's RoT IP.

• Integration Areas: RoT for Attestation (TPM), Update, Recovery; BMC; CPU; Networking (NIC, TPU interconnect); Accelerators (GPU, TPU); BMC/AMC; Storage devices OCP L.O.C.K.

eMemory for AI Servers and Edge Devices

• AI Servers: Storage (SSD Controller, SSD), Processing - Serial (SRAM, CPU, CXL Controller, CXL Memory Expander), Processing - Parallel (GPU).
• AI Edge Computing: SoC (SRAM, CPU, Hardware Root of Trust (PUFrt), Accelerator, Sensors, Actuators), SSD, DRAM, Flash.
• Key Contributions:
  • Memory Repair: For SRAM, DRAM.
  • Root of Trust: Key storage/generation, Cryptographic processing to protect AI models, input data and output results, Confidential Computing.
  • OTP: Needed for trimming analog circuits in Sensors and Actuators.
  • NeoFlash: To replace conventional eFlash for a much lower cost.

eMemory enables High-Yielding SRAM

eMemory's OTP enables high-density SRAM Repair, addressing scaling challenges at advanced nodes.

• Process: Obtains and stores location of bad memory cell in eMemory OTP / eFuse, takes redundant memory column to replace bad cell, replaces and "switches" with bad memory cell.
• Smaller OTP size compared to eFuse: NeoFuse offers 64Kb (0.1mm²) compared to eFuse 64Kb (>1mm²). Repair needs 16256Kb OTP!

eMemory and Siemens: Partnering for Success

eMemory provides OTP with interface for Siemens MBIST.

• Partnership Components: Siemens Tessent (BIST, BIRA, BISR) + FuseBox (eMemory NeoFuse) + RAM (Main Array, Repair Row/Column).
• Key Points:
  • Tessent: Provides memory BISR functions with BIST and BIRA.
  • NeoFuse OTP: Provides defect-free OTP using BIRA, BISR and adapter to Tessent.
  • New MBISR: Tessent MBISR + NeoFuse, scanning defective SRAM by word/column and logging to the OTP.
• Benefits: 1. Compact, 2. Flexible, 3. Robust.
• Definitions: BIST = Built-in Self Test, BIRA = Built-In Redundancy Analysis, BISR = Memory Built-in Self Repair.

NeoPUF-based HSM Edge Server

eMemory embeds a physical unclonable root to secure hardware security module (HSM) infrastructure against hardware tampering and insider threats.

• Components: NeoPUF-based Security IPs (NeoPUF, PUFrt, PUFcc, PUFPQC) -> NeoPUF-based Secure Element Chip (PUFse) (PCIe Card Prototype) -> NeoPUF-based Crypto Engine Accelerator -> NeoPUF-based HSM Edge Server.

NeoPUF-Based Hardware Security as a Service

eMemory extends the physical root of trust to software platforms, enabling automated security provisioning for service workflows.

• Client-Side Devices: PUF-based FIDO, Bio-MFA, Smart Card (PUF Secure).
• SaaS Application Layer (Enterprises, End Customer): Corporate Bitcoin Reserve, Bank Bitcoin Custody, Prokey Ordering System, Self-Signed CA Service, RWA Service, OTA Service, VIP Privacy Protection System, Traceability Service, More Applications...
• Security Capability Layer: PKI (certificate management), IAM (RBAC), KMS (key management), FIDO2 (WebAuthn), CMS (certificate lifecycle).
• Infra. Layer: PUF-based Network HSM (PUF-based HSM Card & Server Integration).

NeoPUF Safeguards National Security

eMemory establishes a non-replicable hardware identity to protect mission-critical defense supply chains.

• Actions: Create a unique and unclonable hardware identity for every chip; Establish a hardware root-of-trust, enabling secure key generation and device authentication; Transform drones, radios, and satellites into trusted and traceable elements of the mission system.

NeoPUF Authenticates Defense Applications

eMemory deploys multi-level hardware security to ensure operational integrity from devices to global supply chains.

• Supply Chain Level: Enforces Global Traceability (Anti-Counterfeiting for Military Electronics, Supply Chain Security).
• System Level: Guarantees Operational Integrity (Secure Boot & Firmware Integrity, IoT & Sensor Network Security).
• Device Level: Establishes Hardware Root-of-Trust (Device Authentication & Identification, Secure Key Generation).

Additional Data

Registered IPs at TSMC

eMemory integrates widely across TSMC process nodes with over 850 registered IPs to enable broad customer adoption.

• IP Portfolio Trend (Unit: # of IPs):
  • 2005: ~50 IPs
  • 2010: ~150 IPs
  • 2015: ~300 IPs
  • 2020: ~600 IPs
  • 2025 (Forecast): ~900 IPs
• Process Nodes: 3nm, 5-4nm, 7-6nm, 16-12nm, 28-22nm, 45-40nm, 65-55nm, 90-80nm, 0.13-0.11um, 0.18-0.14um, 0.25-0.2um, 0.35-0.3um, > 0.35um.

New Tape-Outs at TSMC

eMemory secures continuous success with over 2,600 new tape-outs (NTOs) across all leading-edge and mature process nodes.

• New Tape-out Trend (Unit: # of tape-outs):
  • 2005: <100 NTOs
  • 2010: ~300 NTOs
  • 2015: ~700 NTOs
  • 2020: ~1600 NTOs
  • 2025 (Forecast): ~2700 NTOs
• Process Nodes: 3nm, 5-4nm, 7-6nm, 16-12nm, 28-22nm, 45-40nm, 65-55nm, 90-80nm, 0.13-0.11um, 0.18-0.14um, 0.25-0.2um, 0.35-0.3um, > 0.35um.

Wafer Shipment at TSMC

eMemory translates over 25M wafer shipments (8"-equivalent) into recurring royalty revenue with long-term visibility.

• Wafer Shipment Trend (Unit: M Wafers):
  • 2005: <1 M Wafers
  • 2010: ~2 M Wafers
  • 2015: ~8 M Wafers
  • 2020: ~20 M Wafers
  • 2025 (Forecast): ~32 M Wafers
• Process Nodes: 7-6nm, 16-12nm, 28-22nm, 45-40nm, 65-55nm, 90-80nm, 0.13-0.11um, 0.18-0.14um, 0.25-0.2um, 0.35-0.3um, > 0.35um.

Accumulated Advanced-Node Licensed NTOs

eMemory secures future growth with over 150 advanced-node tape-out licenses, building a high-value royalty pipeline driven by increasing adoption.

• Leading-Edge Nodes (3nm-7nm): 70 TOTAL TAPE-OUTS
  • By Application: HPC and Data Center (41), Consumer Electronics (20), Automotive (5), Industrial and Robotics (3), Others (1).
  • By Chip Type: FPGA (21), CPU/GPU/DPU (11), SSD Controller (8), Retimer (4), ADAS (3), Others (23).
• Mainstream Advanced Nodes (12nm/16nm): 88 TOTAL TAPE-OUTS
  • By Application: Consumer Electronics (58), Industrial and Robotics (8), Smartphone (7), HPC and Data Center (7), Automotive (6), Others (2).
  • By Chip Type: SoC (16), Ethernet IC (14), SSD Controller (11), DDI (6), ASIC (5), Others (36).

Tape-outs and Revenue by Technology

(Revenue includes both licensing and royalty)

eMemory Video Insight: Security in Action

• NeoPUF – The Holy Grail of Security: Establishing an unforgeable identity for every chip, creating the ultimate foundation for zero-trust security.
• Quantum-Proof Security: PUF based HSM Edge Server for PQC Migration: Transforming hardware security into a scalable service, protecting critical data and infrastructure from cloud to edge.
• Chiplet Supply Chain Secured by NeoPUF: Extending trust boundaries to secure the future of heterogeneous computing and integration.
• NeoPUF: The Hardware Trust Anchor Powering Tomorrow's Defense Systems: Powering the trusted core of next-generation defense security.

Contact Information

• eMemory Website: https://www.ememory.com.tw/
• PUFsecurity Website: https://www.pufsecurity.com/